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general description the max11626?ax11629/MAX11632/max11633 are serial 12-bit analog-to-digital converters (adcs) with an internal reference. these devices feature on-chip fifo, scan mode, internal clock mode, internal averaging, and autoshutdown. the maximum sampling rate is 300ksps using an external clock. the MAX11632/ max11633 have 16 input channels; the max11628/ max11629 have 8 input channels; and the max11626/ max11627 have 4 input channels. these eight devices operate from either a +3v supply or a +5v supply, and contain a 10mhz spi-/qspi-/microwire-com- patible serial port. the max11626?ax11629 are available in 16-pin qsop packages. the MAX11632/max11633 are avail- able in 24-pin qsop packages. all eight devices are specified over the extended -40? to +85? tempera- ture range. ________________________applications system supervision data-acquisition systems industrial control systems patient monitoring data logging instrumentation features analog multiplexer with track/hold 16 channels (MAX11632/max11633) 8 channels (max11628/max11629) 4 channels (max11626/max11627) single supply 2.7v to 3.6v (max11627/max11629/max11633) 4.75v to 5.25v (max11626/max11628/MAX11632) internal reference 2.048v (max11627/max11629/max11633) 4.096v (max11626/max11628/MAX11632) external reference: 1v to v dd 16-entry first-in/first-out (fifo) scan mode, internal averaging, and internal clock accuracy: 1 lsb inl, 1 lsb dnl, no missing codes over temperature 10mhz 3-wire spi-/qspi-/microwire-compatible interface small packages 16-pin qsop (max11626Cmax11629) 24-pin qsop (MAX11632/max11633) max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 2 1 3 4 5 6 7 8 ain0 top view eoc dout din cs sclk v dd gnd ref max11626 max11629 qsop ain1 ain2 ain5 (n.c.) ain3 ain4 (n.c.) ain6 (n.c.) ain7/(cnvst) () max11626/max11627 only + pin configurations 19-5323; rev 0; 6/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information + denotes a lead(pb)-free/rohs-compliant package. * future product?ontact for availability. part number of inputs supply voltage range (v) pin package max11626 eee+* 4 4.75 to 5.25 16 qsop max11627 eee+* 4 2.7 to 3.6 16 qsop max11628 eee+* 8 4.75 to 5.25 16 qsop max11629 eee+* 8 2.7 to 3.6 16 qsop MAX11632 eeg+ 16 4.75 to 5.25 24 qsop max11633 eeg+ 16 2.7 to 3.6 24 qsop pin configurations continued at end of data sheet. autoshutdown is a trademark of maxim integrated products, inc. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. note: all devices are specified over the -40? to +85? operating temperature range.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +3.6v (max11627/max11629/max11633); v dd = +4.75v to +5.25v (max11626/max11628/MAX11632), f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v (max11627//max11629/max11633); v ref = 4.096v (max11626/max11628/ MAX11632), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v cs , sclk, din, eoc , dout to gnd.........-0.3v to (v dd + 0.3v) ain0?in13, ain_, cnvst/ ain_, ref to gnd ...........................................-0.3v to (v dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 16-pin qsop (derate 8.3mw/? above +70?)...........667mw 24-pin qsop (derate 9.5mw/? above +70?)...........762mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc accuracy (note 1) resolution res 12 bits integral nonlinearity inl 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1.0 lsb offset error 0.5 4.0 lsb gain error (note 2) 0.5 4.0 lsb offset error temperature coefficient 2 ppm/c fsr gain temperature coefficient 0.8 ppm/c channel-to-channel offset matching 0.1 lsb dynamic specifications (30khz sine-wave input, 2.5v p-p , 300ksps, f sclk = 4.8mhz) max11627/max11629/max11633 71 signal-to-noise plus distortion sinad max11626/max11628/MAX11632 73 db max11627/max11629/ max11633 -80 total harmonic distortion thd up to the 5th harmonic max11626/max11628/ MAX11632 -88 dbc max11627/max11629/max11633 81 spurious-free dynamic range sfdr max11626/max11628/MAX11632 89 dbc intermodulation distortion imd f in1 = 29.9khz, f in2 = 30.2khz 76 dbc full-power bandwidth -3db point 1 mhz full-linear bandwidth s/(n + d) > 68db 100 khz
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +3.6v (max11627/max11629/max11633); v dd = +4.75v to +5.25v (max11626/max11628/MAX11632), f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v (max11627//max11629/max11633); v ref = 4.096v (max11626/max11628/ MAX11632), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units conversion rate external reference 0.8 power-up time t pu internal reference (note 3) 65 s acquisition time t acq 0.6 s internally clocked 3.5 conversion time t conv externally clocked (note 4) 2.7 s externally clocked conversion 0.1 4.8 external clock frequency f sclk data i/o 10 mhz aperture delay 30 ns aperture jitter < 50 ps analog input input voltage range unipolar 0 v ref v input leakage current v in = v dd 0.01 1 a input capacitance during acquisition time (note 5) 24 pf internal reference max11626/max11628/MAX11632 4.024 4.096 4.168 ref output voltage max11627/max11629/max11633 2.48 2.50 2.52 v max11626/max11628/MAX11632 20 ref temperature coefficient tc ref max11627/max11629/max11633 30 ppm/c output resistance 6.5 k ref output noise 200 v rms ref power-supply rejection psrr -70 db external reference input ref input voltage range v ref 1.0 v dd + 50mv v v ref = 2.5v (max11627/max11629/ max11633); v ref = 4.096v (max11626/max11628/MAX11632), f sample = 300ksps 40 100 ref input current i ref v ref = 2.5v (max11627/max11629/ max11633); v ref = 4.096v (max11626/max11628/MAX11632), f sample = 0 0.1 5 a
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 4 _______________________________________________________________________________________ note 1: max11627/max11629/max11633 tested at v dd = +3v. max11626/max11628/MAX11632 tested at v dd = +5v. note 2: offset nulled. note 3: time for reference to power up and settle to within 1 lsb. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 5: see figure 3 (equivalent input circuit) and the sampling error vs. source impedance curve in the typical operating characteristics section. note 6: supply current is specified depending on whether an internal or external reference is used for voltage conversions. electrical characteristics (continued) (v dd = +2.7v to +3.6v (max11627/max11629/max11633); v dd = +4.75v to +5.25v (max11626/max11628/MAX11632), f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v (max11627//max11629/max11633); v ref = 4.096v (max11626/max11628/ MAX11632), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital inputs (sclk, din, cs , cnvst) max11626/max11628/MAX11632 0.8 input voltage low v il max11627/max11629/max11633 v dd x 0.3 v max11626/max11628/MAX11632 2.0 input voltage high v ih max11627/max11629/max11633 v dd x 0.7 v input hysteresis v hyst 200 mv input leakage current i in v in = 0v or v dd 0.01 1.0 a input capacitance c in 15 pf digital outputs (dout, eoc) i sink = 2ma 0.4 output voltage low v ol i sink = 4ma 0.8 v output voltage high v oh i source = 1.5ma v dd - 0.5 v three-state leakage current i l cs = v dd 0.05 1 a three-state output capacitance c out cs = v dd 15 pf power requirements max11626/max11628/MAX11632 4.75 5.25 supply voltage v dd max11627/max11629/max11633 2.7 3.6 v f sample = 300ksps 1750 2000 f sample = 0, ref on 1000 1200 internal reference shutdown 0.2 5 f sample = 300ksps 1050 1200 max11627/max11629/max11633 supply current (note 6) i dd external reference shutdown 0.2 5 a f sample = 300ksps 2300 2550 f sample = 0, ref on 1050 1350 internal reference shutdown 0.2 5 f sample = 300ksps 1550 1700 max11626/max11628/MAX11632 supply current (note 6) i dd external reference shutdown 0.2 5 a v dd = 2.7v to 3.6v; full-scale input 0.2 1 power-supply rejection psr v dd = 4.75v to 5.25v; full-scale input 0.2 1.2 mv
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units externally clocked conversion 208 sclk clock period t cp data i/o 100 ns sclk pulse width high t ch 40 ns sclk pulse width low t cl 40 ns sclk fall to dout transition t dot c load = 30pf 40 ns cs rise to dout disable t dod c load = 30pf 40 ns cs fall to dout enable t doe c load = 30pf 40 ns din to sclk rise setup t ds 40 ns sclk rise to din hold t dh 0 ns cs low to sclk setup t css0 40 ns cs high to sclk setup t css1 40 ns cs high after sclk hold t csh1 0 ns cs low after sclk hold t csh0 0 4 s t cspw cksel = 00 40 ns cnvst pulse width low cksel = 01 1.4 s voltage conversion 7 cs or cnvst rise to eoc low (note 7) reference power-up 65 s timing characteristics (figure 1) (v dd = +2.7v to +3.6v (max11627/max11629/max11633); v dd = +4.75v to +5.25v (max11626/max11628/MAX11632), f sample = 300khz, f sclk = 4.8mhz (50% duty cycle), v ref = 2.5v (max11627//max11629/max11633); v ref = 4.096v (max11626/ max11628/MAX11632), t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) integral nonlinearity vs. output code max11626 toc01 output code (decimal) inl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11626/max11628/MAX11632 f sample = 300ksps integral nonlinearity vs. output code max11626 toc02 output code (decimal) inl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11627/max11629/max11633 f sample = 300ksps differential nonlinearity vs. output code max11626 toc03 output code (decimal) dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11626/max11628/MAX11632 f sample = 300ksps typical operating characteristics (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25?, unless otherwise noted.) note 7: this time is defined as the number of clock cycles needed for conversion multiplied by the clock period. if the internal refer- ence needs to be powered up, the total time is additive.
supply current vs. supply voltage max11626 toc10 v dd (v) i dd (a) 5.15 4.85 5.05 4.95 1200 1400 1600 1800 2000 2200 2400 2600 1000 4.75 5.25 max11626/max11628/MAX11632 f sample = 300ksps internal reference external reference max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 6 _______________________________________________________________________________________ differential nonlinearity vs. output code max11626 toc04 output code (decimal) dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11627/max11629/max11633 f sample = 300ksps sinad vs. frequency max11626 toc05 frequency (khz) sinad (db) 100 10 55 60 65 70 75 80 50 1 1000 max11627/max11629/max11633 max11626/max11628/MAX11632 sfdr vs. frequency max11626 toc06 frequency (khz) sfdr (db) 100 10 60 70 80 90 100 50 11000 max11627/max11629/max11633 max11626/max11628/ MAX11632 thd vs. frequency max11626 toc07 frequency (khz) thd (db) 100 10 -90 -80 -70 -60 -50 -100 1 1000 max11626/max11628/MAX11632 max11627/max11629/max11633 supply current vs. sampling rate max11626 toc08 sampling rate (ksps) i vdd (a) 100 10 500 1000 1500 2000 2500 3000 0 11000 max11626/max11628/MAX11632 v dd = 5v internal reference external reference supply current vs. sampling rate max11626 toc09 sampling rate (ksps) i vdd (a) 100 10 200 400 600 800 1000 1200 1400 1600 1800 0 1 1000 max11627/max11629/max11633 v dd = 3v internal reference external reference typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25?, unless otherwise noted.)
max11626?ax11629/MAX11632/max11633 v dd (v) i dd (a) supply current vs. supply voltage max11626 toc11 3.5 3.6 3.3 3.4 2.9 3.0 3.1 3.2 2.8 200 400 600 800 1000 1200 1400 1600 1800 2000 0 2.7 max11627/max11629/max11633 f sample = 300ksps internal reference external reference shutdown supply current vs. supply voltage max11626 toc12 v dd (v) i dd (a) 5.15 4.85 5.05 4.95 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 4.75 5.25 max11626/max11628/MAX11632 v dd = 5v shutdown supply current vs. supply voltage max11626 toc13 v dd (v) i dd (a) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 0.1 0.2 0.3 0.4 0.5 0 2.7 3.6 max11627/max11629/max11633 v dd = 3v supply current vs. temperature max11626 toc14 temperature (c) i dd (a) 60 35 10 -15 1300 1600 1900 2200 2500 1000 -40 85 max11626/max11628/MAX11632 v dd = 5v f sample = 300ksps internal reference external reference supply current vs. temperature max11626 toc15 temperature (c) i dd (a) 60 35 10 -15 800 1000 1200 1400 1600 1800 600 -40 85 max11627/max11629/max11633 v dd = 3v f sample = 300ksps internal reference external reference 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25?, unless otherwise noted.) shutdown supply current vs. temperature max11626 toc16 temperature (c) i dd (a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 0 -40 85 max11626/max11628/MAX11632 v dd = 5v
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 8 _______________________________________________________________________________________ internal reference voltage vs. temperature max11626 toc20 temparature (c) v ref (v) 60 35 10 -15 4.08 4.09 4.10 4.11 4.12 4.07 -40 85 max11626/max11628/MAX11632 v dd = 5v internal reference voltage vs. temperature max11626 toc21 temparature (c) v ref (v) 60 35 10 -15 2.48 2.49 2.50 2.51 2.52 2.47 -40 85 max11627/max11629/max11633 v dd = 3v offset error vs. supply voltage max11626 toc22 v dd (v) offset error (lsb) 5.15 5.05 4.95 4.85 -0.4 -0.2 0 0.2 0.4 0.6 -0.6 4.75 5.25 max11626/max11628/MAX11632 f sample = 300ksps offset error vs. supply voltage max11626 toc23 v dd (v) offset error (lsb) 3.3 3.0 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.00 2.7 3.6 max11627/max11629/max11633 f sample = 300ksps offset error vs. temperature max11626 toc24 temperature (c) offset error (lsb) 60 35 10 -15 -0.6 -0.2 0.2 0.6 1.0 -1.0 -40 85 max11626/max11628/MAX11632 f sample = 300ksps offset error vs. temperature max11626 toc25 temperature (c) offset error (lsb) 60 35 10 -15 0.7 0.9 1.1 1.3 1.5 0.5 -40 85 max11627/max11629/max11633 f sample = 300ksps shutdown supply current vs. temperature max11626 toc17 temperature (c) i dd (a) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 max11627/max11629/max11633 v dd = 3v internal reference voltage vs. supply voltage max11626 toc18 v dd (v) v ref (v) 5.15 5.05 4.95 4.85 4.095 4.096 4.097 4.098 4.099 4.094 4.75 5.25 max11626/max11628/MAX11632 v dd = 5v internal reference voltage vs. supply voltage max11626 toc19 v dd (v) v ref (v) 3.3 3.0 2.498 2.499 2.500 2.501 2.502 2.497 2.7 3.6 max11627/max11629/max11633 v dd = 3v typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25?, unless otherwise noted.)
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference _______________________________________________________________________________________ 9 gain error vs. supply voltage max11626 toc26 v dd (v) gain error (lsb) 5.15 5.05 4.95 4.85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 4.75 5.25 max11626/max11628/MAX11632 f sample = 300ksps gain error vs. supply voltage max11626 toc27 v dd (v) gain error (lsb) 3.3 3.0 -0.4 -0.3 -0.2 -0.1 0 -0.5 2.7 3.6 max11627/max11629/max11633 gain error vs. temperature max11626 toc28 temperature (c) gain error (lsb) 60 35 10 -15 -0.6 -0.2 0.2 0.6 1.0 -1.0 -40 85 max11626/max11628/MAX11632 f sample = 300ksps gain error vs. temperature max11626 toc29 temperature (c) gain error (lsb) 60 35 10 -15 -0.3 -0.1 0.1 0.3 0.5 -0.5 -40 85 max11627/max11629/max11633 f sample = 300ksps -10 -6 -8 -2 -4 0 2 04 26810 sampling error vs. source impedance max11626 toc30 source impedance (k ) sampling error (lsb) typical operating characteristics (continued) (v dd = +3v, v ref = +2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25?, unless otherwise noted.)
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 10 ______________________________________________________________________________________ pin description max11626 max11627 (4 channels) max11628 max11629 (8 channels) MAX11632 max11633 (16 channels) name function 5, 6, 7 n.c. no connection. not internally connected. 1?5 ain0?in14 analog inputs 1? ain0?in6 analog inputs 1? ain0?in3 analog inputs 16 cnvst /ain15 active-low conversion start input/analog input 15. see table 3 for details on programming the setup register. ? cnvst /ain7 active-low conversion start input/analog input 7. see table 3 for details on programming the setup register. 8 cnvst active-low conversion start input. see table 3 for details on programming the setup register. 9 9 17 ref reference input. bypass to gnd with a 0.1? capacitor. 10 10 18 gnd ground 11 11 19 v dd power input. bypass to gnd with a 0.1? capacitor. 12 12 20 cs active-low chip-select input. when cs is low, the serial interface is enabled. when cs is high, dout is high impedance. 13 13 21 sclk s er i al c l ock inp ut. c l ocks d ata i n and out of the ser i al i nter face. ( d uty cycl e m ust b e 40% to 60% .) s ee tab l e 3 for d etai l s on p r og r am m i ng the cl ock m od e. 14 14 22 din serial data input. din data is latched into the serial interface on the rising edge of sclk. 15 15 23 dout s er i al d ata outp ut. d ata i s cl ocked out on the fal l i ng ed g e of s c lk. h i g h i m p ed ance w hen cs i s connected to v d d . 16 16 24 eoc end of conversion output. data is valid after eoc pulls low.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 11 detailed description the max11626?ax11629/MAX11632/max11633 are low-power, serial-output, multichannel adcs with fifo capability for system monitoring, process-control, and instrumentation applications. these 12-bit adcs have internal track and hold (t/h) circuitry supporting single- ended inputs. data is converted from analog voltage sources in a variety of channel and data-acquisition con- figurations. microprocessor (?) control is made easy through a 3-wire spi-/qspi-/microwire-compatible serial interface. figure 2 shows a simplified functional diagram of the max11626?ax11629/MAX11632/max11633 internal architecture. the MAX11632/max11633 have 16 sin- gle-ended analog input channels. the max11628/ max11629 have 8 single-ended analog input channels. the max11626/max11627 have 4 single-ended analog input channels. sclk din dout cs t dh t doe t ds t ch t cl t css0 t cp t csh1 t csh0 t css1 t dod t dot figure 1. detailed serial-interface timing diagram 12-bit sar adc control serial interface oscillator fifo and accumulator t/h cnvst sclk cs din eoc dout ain15 ain1 ain2 internal reference ref max11626?ax11629/MAX11632/max11633 figure 2. functional diagram
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 12 ______________________________________________________________________________________ converter operation the max11626?ax11629/MAX11632/max11633 adcs use a successive-approximation register (sar) conversion technique and an on-chip t/h block to con- vert voltage signals into a 12-bit digital result. this sin- gle-ended configuration supports unipolar signal ranges. input bandwidth the adc? input-tracking circuitry has a 1mhz small- signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. analog input protection internal esd protection diodes clamp all pins to v dd and gnd, allowing the inputs to swing from (gnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if an off-channel analog input voltage exceeds the supplies, limit the input current to 2ma. 3-wire serial interface the max11626?ax11629/MAX11632/max11633 fea- ture a serial interface compatible with spi/qspi and microwire devices. for spi/qspi, ensure the cpu serial interface runs in master mode so it generates the serial clock signal. select the sclk frequency of 10mhz or less, and set clock polarity (cpol) and phase (cpha) in the ? control registers to the same value. the max11626?ax11629/MAX11632/max11633 oper- ate with sclk idling high or low, and thus operate with cpol = cpha = 0 or cpol = cpha = 1. set cs low to latch input data at din on the rising edge of sclk. output data at dout is updated on the falling edge of sclk. results are output in binary format. serial communication always begins with an 8-bit input data byte (msb first) loaded from din. a high-to-low transition on cs initiates the data input operation. the input data byte and the subsequent data bytes are clocked from din into the serial interface on the rising edge of sclk. tables 1? detail the register descrip- tions. bits 5 and 4, cksel1 and cksel0, respectively, control the clock modes in the setup register (see table 3). choose between four different clock modes for vari- ous ways to start a conversion and determine whether the acquisitions are internally or externally timed. select clock mode 00 to configure cnvst /ain_ to act as a conversion start and use it to request the programmed, internally timed conversions without tying up the serial bus. in clock mode 01, use cnvst to request conver- sions one channel at a time, controlling the sampling speed without tying up the serial bus. request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. use clock mode 11 with sclk up to 4.8mhz for externally timed acquisitions to achieve sampling rates up to 300ksps. clock mode 11 disables scanning and averaging. see figures 4? for timing specifications and how to begin a conversion. these devices feature an active-low, end-of-conversion output. eoc goes low when the adc completes the last requested operation and is waiting for the next input data byte (for clock modes 00 and 10). in clock mode 01, eoc goes low after the adc completes each requested operation. eoc goes high when cs or cnvst goes low. eoc is always high in clock mode 11. single-ended inputs the single-ended analog input conversion modes can be configured by writing to the setup register (see table 3). single-ended conversions are internally refer- enced to gnd (see figure 3). ain0?in3 are available on the max11626?ax11629/ MAX11632/max11633. ain4?in7 are only available on the max11628?ax11633. ain8?in15 are only avail- able on the MAX11632/max11633. see tables 2? for more details on configuring the inputs. for the inputs that can be configured as cnvst or an analog input, only one can be used at a time. unipolar the max11626?ax11629/MAX11632/max11633 always operate in unipolar mode. the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . + - hold cin+ ref gnd dac cin- v dd /2 comparator ain0-ain15 gnd hold hold figure 3. equivalent input circuit
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 13 true differential analog input t/h the equivalent circuit of figure 3 shows the max11626?ax11629/MAX11632/max11633? input architecture. in track mode, a positive input capacitor is connected to ain0?in15. a negative input capacitor is connected to gnd. for external t/h timing, use clock mode 01. after the t/h enters hold mode, the difference between the sampled positive and negative input volt- ages is converted. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. if the input signal? source impedance is high, the required acquisition time lengthens. the acquisition time, t acq , is the maximum time needed for a signal to be acquired, plus the power-up time. it is calculated by the following equa- tion: t acq = 9 x (r s + r in ) x 24pf + t pwr where r in = 1.5k , r s is the source impedance of the input signal, and t pwr = 1?, the power-up time of the device. the varying power-up times are detailed in the explanation of the clock mode conversions. t acq is never less than 1.4?, and any source impedance below 300 does not significantly affect the adc? ac performance. a high-impedance source can be accommodated either by lengthening t acq or by placing a 1? capacitor between the positive and negative analog inputs. internal fifo the max11626?ax11629/MAX11632/max11633 con- tain a fifo buffer that can hold up to 16 adc results. this allows the adc to handle multiple internally clocked conversions, without tying up the serial bus. if the fifo is filled and further conversions are requested without reading from the fifo, the oldest adc results are over- written by the new adc results. each result contains 2 bytes, with the msb preceded by four leading zeros. after each falling edge of cs , the oldest available byte of data is available at dout, msb first. when the fifo is empty, dout is zero. internal clock the max11626?ax11629/MAX11632/max11633 oper- ate from an internal oscillator, which is accurate within 10% of the 4.4mhz nominal clock rate. the internal oscillator is active in clock modes 00, 01, and 10. read out the data at clock speeds up to 10mhz. see figures 4? for details on timing specifications and starting a conversion. applications information register descriptions the max1 1626?ax11629/max116 32/max11633 com- municate between the internal registers and the exter- nal circuitry through the spi-/qspi-compatible serial interface. table 1 details the registers and the bit names. tables 2? show the various functions within the conversion register, setup register, averaging regis- ter, and reset register. conversion time calculations the conversion time for each scan is based on a num- ber of different factors: conversion time per sample, samples per result, results per scan, and if the external reference is in use. use the following formula to calculate the total conver- sion time for an internally timed conversion in clock modes 00 and 10 (see the electrical characteristics section as applicable): total conversion time = t cnv x n avg x n result + t rp where t cnv = t acq (max) + t conv (max). n avg = samples per result (amount of averaging). n result = number of fifo results requested; determined by the number of channels being scanned or by nscan1, nscan0. t rp = internal reference wake-up; set to zero if inter- nal reference is already powered up or external ref- erence is being used . in clock mode 01, the total conversion time depends on how long cnvst is held low or high, including any time required to turn on the internal reference. conversion time in externally clocked mode (cksel1, cksel0 = 11) depends on the sclk period and how long cs is held high between each set of eight sclk cycles. in clock mode 01, the total conversion time does not include the time required to turn on the internal reference. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 conversion 1 chsel3 chsel2 chsel1 chsel0 scan1 scan0 x setup 0 1 cksel1 cksel0 refsel1 refsel0 x x averaging 0 0 1 avgon navg1 navg0 nscan1 nscan0 reset 0001 reset xxx table 1. input data byte (msb first) x = don? care.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 14 ______________________________________________________________________________________ conversion register select active analog input channels per scan and scan modes by writing to the conversion register. table 2 details channel selection and the four scan modes. request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the cnvst pin when in clock mode 00 or 01. a conversion is not performed if it is requested on a channel that has been configured as cnvst . do not request conversions on channels 8?5 on the max11626?ax11629. set chsel3:chsel0 to the lower channel? binary values. select scan mode 00 or 01 to return one result per sin- gle-ended channel within the requested range. select scan mode 10 to scan a single input channel numerous times, depending on nscan1 and nscan0 in the averaging register (table 4). select scan mode 11 to return only one result from a single channel. setup register write a byte to the setup register to configure the clock, reference, and power-down modes. table 3 details the bits in the setup register. bits 5 and 4 (cksel1 and cksel0) control the clock mode, acquisition and sam- pling, and the conversion start. bits 3 and 2 (refsel1 and refsel0) control internal or external reference use. averaging register write to the averaging register to configure the adc to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. table 2 details the four scan modes available in the conversion register. all four scan modes allow averag- ing as long as the avgon bit, bit 4 in the averaging register, is set to 1. select scan mode 10 to scan the same channel multiple times. clock mode 11 disables averaging. reset register write to the reset register (as shown in table 5) to clear the fifo or to reset all registers to their default states. set the reset bit to 1 to reset the fifo. set the reset bit to zero to return the max11626?ax11629/ MAX11632/max11633 to the default power-up state. bit name bit function 7 (msb) set to 1 to select conversion register. chsel3 6 analog input channel select. chsel2 5 analog input channel select. chsel1 4 analog input channel select. chsel0 3 analog input channel select. scan1 2 scan mode select. scan0 1 scan mode select. 0 (lsb) don? care. table 2. conversion register* *see below for bit details. chsel3 chsel2 chsel1 chsel0 selected channel (n) 0 0 0 0 ain0 0 0 0 1 ain1 0 0 1 0 ain2 0 0 1 1 ain3 0 1 0 0 ain4 0 1 0 1 ain5 0 1 1 0 ain6 0 1 1 1 ain7 1 0 0 0 ain8 1 0 0 1 ain9 1 0 1 0 ain10 1 0 1 1 ain11 1 1 0 0 ain12 1 1 0 1 ain13 1 1 1 0 ain14 1 1 1 1 ain15 scan1 scan0 scan mode (channel n is selected by bits chsel3?hsel0) 0 0 scans channels 0 through n. 01 scans channels n through the highest numbered channel. 10 s cans channel n r ep eated l y. the aver ag i ng r eg i ster sets the num b er of r esul ts. 1 1 no scan. converts channel n once only.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 15 table 3. setup register* bit name bit function 7 (msb) set to 0 to select setup register. 6 set to 1 to select setup register. cksel1 5 clock mode and cnvst configuration. resets to 1 at power-up. cksel0 4 clock mode and cnvst configuration. refsel1 3 reference mode configuration. refsel0 2 reference mode configuration. 1 don? care. 0 (lsb) don? care. cksel1 cksel0 conversion clock acquisition/sampling cnvst configuration 0 0 internal internally timed cnvst 0 1 internal externally timed through cnvst cnvst 1 0 internal internally timed ain15/ain11/ain7* 1 1 external (4.8mhz max) externally timed through sclk ain15/ain11/ain7* refsel1 refsel0 voltage reference autoshutdown 0 0 internal reference off after scan; need wake-up delay. 0 1 external reference off; no wake-up delay. 1 0 internal reference always on; no wake-up delay. 1 1 reserved reserved. do not use. *see below for bit details. *for the max11626/max11627, cnvst has its own dedicated pin.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 16 ______________________________________________________________________________________ avgon navg1 navg0 function 0 x x performs one conversion for each requested result. 1 0 0 performs four conversions and returns the average for each requested result. 1 0 1 performs eight conversions and returns the average for each requested result. 1 1 0 performs 16 conversions and returns the average for each requested result. 1 1 1 performs 32 conversions and returns the average for each requested result. nscan1 nscan0 function (applies only if scan mode 10 is selected) 0 0 scans channel n and returns four results. 0 1 scans channel n and returns eight results. 1 0 scans channel n and returns 12 results. 1 1 scans channel n and returns 16 results. bit name bit function 7 (msb) set to 0 to select reset register. 6 set to 0 to select reset register. 5 set to 0 to select reset register. 4 set to 1 to select reset register. reset 3 set to 0 to reset all registers. set to 1 to clear the fifo only. x 2 reserved. don? care. x 1 reserved. don? care. x 0 (lsb) reserved. don? care. table 5. reset register bit name bit function 7 (msb) set to 0 to select averaging register. 6 set to 0 to select averaging register. 5 set to 1 to select averaging register. avgon 4 set to 1 to turn averaging on. set to 0 to turn averaging off. navg1 3 configures the number of conversions for single-channel scans. navg0 2 configures the number of conversions for single-channel scans. nscan1 1 single-channel scan count. (scan mode 10 only.) nscan0 0 (lsb) single-channel scan count. (scan mode 10 only.) table 4. averaging register* *see below for bit details.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 17 power-up default state the max11626?ax11629/MAX11632/max11633 power up with all blocks in shutdown, including the ref- erence. all registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (cksel1 = 1) output data format figures 4? illustrate the conversion timing for the max11626?ax11629/MAX11632/max11633. the 12-bit conversion result is output in msb-first format with four leading zeros. din data is latched into the ser- ial interface on the rising edge of sclk. data on dout transitions on the falling edge of sclk. conversions in clock modes 00 and 01 are initiated by cnvst . conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. data output is binary. internally timed acquisitions and conversions using cnvst performing conversions in clock mode 00 in clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through cnvst and performed automatically using the internal oscilla- tor. results are added to the internal fifo to be read out later. see figure 4 for clock mode 00 timing. initiate a scan by setting cnvst low for at least 40ns before pulling it high again. the max11626?ax11629/ MAX11632/max11633 then wake up, scan all request- ed channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. wait until eoc goes low before pulling cs low to communicate with the serial interface. eoc stays low until cs or cnvst is pulled low again. do not initiate a second cnvst before eoc goes low; otherwise, the fifo can become corrupted. externally timed acquisitions and internally timed conversions with cnvst performing conversions in clock mode 01 in clock mode 01, conversions are requested one at a time using cnvst and performed automatically using the internal oscillator. see figure 5 for clock mode 01 timing. setting cnvst low begins an acquisition, wakes up the adc, and places it in track mode. hold cnvst low for at least 1.4? to complete the acquisition. if the internal reference needs to wake up, an additional 65? is required for the internal reference to power up. set cnvst high to begin a conversion. after the con- version is complete, the adc shuts down and pulls eoc low. eoc stays low until cs or cnvst is pulled low again. wait until eoc goes low before pulling cs or cnvst low. if averaging is turned on, multiple cnvst pulses need to be performed before a result is written to the fifo. once the proper number of conversions has been per- formed to generate an averaged fifo result, as speci- fied by the averaging register, the scan logic automatically switches the analog input multiplexer to the next-requested channel. the result is available on dout once eoc has been pulled low. (up to 514 internally clocked acquisitions and conversions) cs dout msb1 lsb1 msb2 sclk cnvst eoc set cnvst low for at least 40ns to begin a conversion. figure 4. clock mode 00 timing
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 18 ______________________________________________________________________________________ cs dout sclk cnvst eoc (conversion2) msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) request multiple conversions by setting cnvst low for each conversion. figure 5. clock mode 01 timing (up to 514 internally clocked acquisitions and conversions) msb1 lsb1 msb2 (conversion byte) cs dout sclk din eoc the conversion byte begins the acquisition. cnvst is not required. figure 6. clock mode 10 timing internally timed acquisitions and conversions using the serial interface performing conversions in clock mode 10 in clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are per- formed automatically using the internal oscillator. this is the default clock mode upon power-up. see figure 6 for clock mode 10 timing. initiate a scan by writing a byte to the conversion regis- ter. the max11626?ax11629/MAX11632/max11633 then power up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are avail- able in the fifo. eoc stays low until cs is pulled low again. externally clocked acquisitions and conversions using the serial interface performing conversions in clock mode 11 in clock mode 11, acquisitions and conversions are ini- tiated by writing to the conversion register and are per- formed one at a time using the sclk as the conversion clock. scanning and averaging are disabled, and the conversion result is available at dout during the con- version. see figure 7 for clock mode 11 timing.
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 19 initiate a conversion by writing a byte to the conversion register followed by 16 sclk cycles. if cs is pulsed high between the eight and ninth cycles, the pulse width must be less than 100?. to continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. if reference mode 00 is requested, wait 65? with cs high after writing the conversion byte to extend the acquisition and allow the internal reference to power up. partial reads and partial writes if the first byte of an entry in the fifo is partially read ( cs is pulled high after fewer than eight sclk cycles), the second byte of data that is read out contains the next 8 bits (not b7?0). the remaining bits are lost for that entry. if the first byte of an entry in the fifo is read out fully, but the second byte is read out partially, the rest of the entry is lost. the remaining data in the fifo is uncorrupted and can be read out normally after tak- ing cs low again, as long as the 4 leading bits (normal- ly zeros) are ignored. internal registers that are written partially through the spi contain new values, starting at the msb up to the point that the partial write is stopped. the part of the register that is not written contains previ- ously written values. if cs is pulled low before eoc goes low, a conversion cannot be completed and the fifo is corrupted. transfer function figure 8 shows the unipolar transfer function. code tran- sitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = v ref /2.5v (max11627/max11629/max11633) and 1 lsb = v ref / 4.096v (max11626/max11628/MAX11632). layout, grounding, and bypassing for best performance, use pcbs. do not use wire wrap boards. board layout should ensure that digital and ana- log signal lines are separated from each other. do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the max11626?ax11629/MAX11632/max11633 package. high-frequency noise in the v dd power supply can affect performance. bypass the v dd supply with a 0.1? capacitor to gnd, close to the v dd pin. minimize capaci- tor lead lengths for best supply-noise rejection. if the power supply is very noisy, connect a 10 resistor in series with the supply to improve power-supply filtering. cs dout sclk din eoc msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) (conversion byte) externally timed acquisition, sampling and conversion without cnvst. figure 7. clock mode 11 timing output code full-scale transition 11 . . . . . . 111 11 . . . . . . 110 11 . . . . . . 101 00 . . . . . . 011 00 . . . . . . 010 00 . . . . . . 001 00 . . . . . . 000 123 0 (com) fs fs - 3/2 lsb fs = v ref + v com zs = v com input voltage (lsb) 1 lsb = v ref 4096 figure 8. unipolar transfer function, full scale (fs) = v ref
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference 20 ______________________________________________________________________________________ definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max11626?ax11629/MAX11632/max11633 is measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all other adc output signals: sinad (db) = 20 x log (signal rms /noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantiza- tion noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v1 is the fundamental amplitude, and v2?5 are the amplitudes of the first five harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest distor- tion component. thd 20 x log v v v v /v 2 2 3 2 4 2 5 2 1 =+++ ? ? ? ? ? ? ? ? ? ?
max11626?ax11629/MAX11632/max11633 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 eoc dout din cs ain3 ain2 ain1 ain0 top view sclk v dd gnd ref ain7 ain6 ain5 ain4 16 15 14 13 9 10 11 12 ain14 cnvst/ain15 ain13 ain12 ain11 ain10 ain9 ain8 qsop MAX11632 max11633 + pin configurations (continued) chip information process: bicmos 12-bit, 300ksps adcs with fifo and internal reference ______________________________________________________________________________________ 21 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 qsop e16+5 21-0055 91-0168 24 qsop e24+1 21-0055 91-0168
max11626?ax11629/MAX11632/max11633 12-bit, 300ksps adcs with fifo and internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products. revision history revision number revision date description pages changed 0 6/10 initial release

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